1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise highly capacitive gate structures including a metal-containing electrode and a high-k gate dielectric of increased permittivity compared to gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits is fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may no longer be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride, aluminum oxide and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since typically a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain the high drive currents, commonly, the controllability of the respective channel requires sophisticated lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll-off, and also reducing significant variations of transistor performance with a variation in gate length. Since the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride, aluminum oxide and the like, may frequently be used, wherein the corresponding work function may be adjusted so as to be appropriate for one type of transistor, such as N-channel transistors, while P-channel transistors may require a different work function and thus a differently treated metal-containing electrode material in order to obtain the desired threshold voltage. In this case, complex and sophisticated manufacturing regimes may be required to provide different gate electrode materials in order to comply with the requirements of different transistor types. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique, which may also present an additional complex process step, which, however, may provide reduced overall process complexity compared to the provision of the different metal-containing gate electrode materials or which may provide increased flexibility in obtaining appropriate transistor characteristics.
It turns out, however, that the manufacturing sequence for providing the threshold adjusting semiconductor alloy may have a significant influence on threshold variability across an active region, as will be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a silicon-containing semiconductor material 103 having an appropriate thickness for forming therein and thereabove transistor elements. In the example shown, a buried insulating layer 102, for instance in the form of a silicon dioxide material, is positioned between the substrate 101 and the silicon-containing semiconductor layer 103. Moreover, an isolation structure 104, such as a shallow trench isolation, is formed in the semiconductor layer 103 to define a first crystalline “active” region 103A and a second active region 103B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is to be created in order to form PN junctions for one or more transistor elements. In the example shown, the first active region 103A may correspond to one or more P-channel transistors while the second active region 103B may correspond to one or more N-channel transistors. Furthermore, in the manufacturing stage shown, a silicon dioxide mask layer 105 is formed above the first and second active regions 103A, 103B, while typically the silicon dioxide material of the layer 105 may not be formed on the isolation structure 104, since typically the material of the layer 105 may be formed as a thermal oxide material.
The semiconductor device 100 as illustrated in FIG. 1a may typically be formed on the basis of the following process techniques. First, the isolation structure 104 is formed on the basis of well-established lithography, etch, deposition, planarization and anneal techniques in which, for instance, a trench is formed in the semiconductor layer 103 on the basis of a lithography process, which is subsequently filled with an appropriate insulating material such as silicon dioxide, silicon nitride and the like. After removing any excess material, further processing is typically continued by performing implantation sequences using an appropriate mask regime in order to introduce the appropriate dopant species for the active regions 103A, 103B. It should be appreciated that, although sophisticated planarization techniques may typically be used during the formation of the isolation structure 104, nevertheless a more or less pronounced surface topography may be obtained after the above-described process sequence so that the material of the active regions 103A, 103B may extend above the surface 104S of the isolation structure 104. Thereafter, the silicon dioxide 105 may be formed, for instance, by oxidation on the basis of appropriately selected process parameters in order to obtain a desired thickness of the layer 105, which may act as a growth mask during the further processing of the semiconductor device 100. That is, as previously discussed, the active region 103A has to be exposed prior to performing a selective epitaxial growth process for depositing a silicon/germanium alloy that may provide the required band gap offset or threshold voltage adjustment for corresponding P-channel transistors to be formed in and above the active region 103A.
FIG. 1b schematically illustrates the semiconductor device in a further advanced manufacturing stage in which a resist mask 106 is formed above the second active region 103B. The resist mask may be formed by lithography techniques in accordance with similar recipes as may also be used for the masking regime when introducing the corresponding well dopant species into the active regions 103A, 103B. Thus, after patterning the resist mask 106, the active region 103A is exposed to a wet chemical etch ambient 107, which may be performed on the basis of hydrofluoric acid (HF), which may efficiently remove silicon dioxide selectively to silicon material. Thus, the exposed portion of the mask layer 105 is effectively removed wherein, however, the previously created surface topography with respect to the regions 103A, 103B and the isolation structure 104 may typically be maintained or may be even further increased. Next, a further wet chemical etch process is typically performed to remove the resist mask 106 on the basis of well-established etch recipes wherein, depending on the chemistry used, the resulting surface topography may further be increased.
FIG. 1c schematically illustrates the semiconductor device 100 after the above-described process sequence and prior to actually depositing the silicon/germanium alloy on the exposed active region 103A. As illustrated, the moderately pronounced surface topography may result in the exposure of a horizontal surface portion 103H and also of a substantially vertical surface portion 103V, wherein both portions may act as deposition surface areas during the subsequent epitaxial growth process.
FIG. 1d schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 108 in which process parameters are selected in accordance with well-established recipes such that a significant material deposition may be restricted to the exposed surface areas 103H, 103V (FIG. 1c), while a material deposition on dielectric surface areas, such as the isolation structure 104 and the silicon dioxide mask layer 105, may be negligible. Consequently, during the selective epitaxial growth process 108 a silicon/germanium alloy 109 may be selectively formed on the active region 103A, wherein the surface portions 103H, 103V may act as a template material. For instance, in sophisticated applications, the silicon/germanium alloy 109 may have to be provided with a desired target thickness, for instance of approximately 10 nm, when a germanium concentration of approximately 25 atomic percent is used. It should be appreciated that the material composition of the silicon/germanium alloy 109 as well as the thickness thereof may have a significant influence on the finally obtained threshold voltage and thus the finally obtained transistor characteristics. Although the material composition may be controlled with a high degree of accuracy, a significant degree of threshold variability may be observed in completed semiconductor devices, which is believed to be caused by a thickness variation in the silicon/germanium alloy. Without intending to restrict the present disclosure to any theory, it is nevertheless assumed that a difference of growth rate may occur during the deposition process 108, which may have its origin in the different crystallographic orientations of the exposed surface areas 103H, 103V. That is, as illustrated in FIG. 1d, the semiconductor layer 103 may be provided as a crystalline material having a surface orientation (100) while a transistor length direction and width directions are typically aligned with respect to the crystallographic <110> direction. Consequently, in particular at the area in the vicinity of the isolation structure 104, in which the surface portion 103V may have a substantially (110) orientation and in the area of a corresponding rounded portion 103R (see FIG. 1c), other crystallographic directions may be present, thereby resulting in an increased growth rate compared to central portions having substantially the (100) orientation. As a consequence, a thickness 109P at the periphery of the active region 103A may be greater compared to a thickness 109C in the center of the active region 103A, thereby possibly resulting in a threshold variability across the active region 103A.
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, one or more P-channel transistors 150A are formed in and above the active region 103A on the basis of respective silicon/germanium alloys, which may be referred to as alloys 109C, 109P, since these materials may have a different thickness, as previously explained with reference to FIG. 1d. Furthermore, an N-channel transistor 150B is formed in and above the active region 103B. The transistors 150A, 150B comprise an electrode structure 151 including a gate insulation layer 151B, comprising a high-k dielectric material, as is previously explained. Furthermore, a metal-containing electrode material, such as aluminum oxide, titanium nitride and the like, may be formed on the gate insulation layer 151B, followed by a further electrode material, such as polysilicon 151C. As illustrated, in the P-channel transistors 150A, the gate insulation layers 151B are formed on the corresponding silicon/germanium alloys 109C, 109P, respectively, so that a threshold voltage of the transistors 150A, i.e., the voltage at which a conductive channel forms in a channel region 153, may be determined by the characteristics of the alloys 109C, 109P and the materials 151B and 151A in combination with the corresponding characteristics of drain and source regions 154, which may also be formed on the basis of sophisticated dopant profiles, as previously explained. On the other hand, the band gap configuration of the channel region 153 of the N-channel transistor 150B is appropriate for the corresponding materials 151B, 151A of the transistor 150B. Thus, in this configuration, although the silicon/germanium alloy may be formed on the basis of a specifically selected target thickness, which may result in substantially the same threshold voltages for transistors 150A, the previously occurring deposition non-uniformity may thus contribute to a corresponding difference in transistor characteristics, even if the remaining manufacturing processes for forming the gate electrode structure 151 and the drain and source regions 154 may be performed with a high degree of process uniformity.
FIG. 1f schematically illustrates a cross-sectional view in order to depict a P-channel transistor, such as one of the transistors 150A of FIG. 1e, along a transistor width direction. Thus, as illustrated, the gate electrode structure 151 may extend across the entire active region 103A and may also be formed above a portion of the isolation structure 104. Due to the deposition non-uniformities previously described, the silicon/germanium alloy 109 may comprise the peripheral portion 109P and the central portion 109C, which may thus differ in thickness, as discussed above. Consequently, also within a single transistor element, a pronounced thickness variation of the silicon/germanium alloy may exist so that an overall threshold voltage may be obtained that may be difficult to be predicted due to the varying thickness of the silicon/germanium alloy 109. Moreover, for a difference in transistor width of various active regions, a further pronounced threshold variability may occur since, for an increased overall transistor width, the edge effect at the isolation structure 104 may be less pronounced compared to a transistor active region having a reduced width. Consequently, the dependence of the threshold voltage on the transistor width may be significantly increased due to the thickness variation of the silicon/germanium material, even within a single transistor element, thereby contributing to a significant overall device variability, which may not be compatible with performance requirements of sophisticated semiconductor devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.